8k x 8 static ram cy6264 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-02367 rev. *a revised august 8, 2006 features ? temperature ranges ? commercial: 0c to 70c ? industrial: ?40c to 85c ? automotive-a: ?40c to 85c ? high speed ? 55 ns ? cmos for optimum speed/power ? easy memory expansion with ce 1 , ce 2 and oe features ? ttl-compatible inputs and outputs ? automatic power-down when deselected ? available in pb-free and non pb-free 28-lead snc package functional description the cy6264 is a high-performance cmos static ram organized as 8192 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce 1 ), an active high chip enable (ce 2 ), and active low output enable (oe ) and three-state drivers. both devices have an automatic power-down feature (ce 1 ), reducing the power consumption by over 70% when deselected. the cy6264 is packaged in a 450-mil (300-mil body) soic. an active low write enable signal (we ) controls the writing/reading operation of the memory. when ce 1 and we inputs are both low and ce 2 is high, data on the eight data input/output pins (i/o 0 through i/o 7 ) is written into the memory location addressed by the address present on the address pins (a 0 through a 12 ). reading the device is accomplished by selecting the device and enabling the outputs, ce 1 and oe active low, ce 2 active high, while we remains inactive or high. under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. the input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (we ) is high. a die coat is used to ensure alpha immunity. pin configuration a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 0 a a 9 i/o 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc we ce 2 a 3 a 2 a 1 oe a 0 ce 1 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 nc a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 i/o 0 i/o 1 i/o 2 gnd 8k x 8 array input buffer column decoder row decoder sense amps power down i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ce 1 ce 2 we oe top view soic logic block diagram 10 11 a 12 a
cy6264 document #: 001-02367 rev. *a page 2 of 9 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage to ground potential ............... ?0.5v to +7.0v dc voltage applied to outputs in high z state [1] ............................................ ?0.5v to +7.0v dc input voltage [1] ......................................... ?0.5v to +7.0v output current into outputs (low)............................. 20 ma static discharge voltage......... ........... ............ ........... >2001v (per mil-std-883, method 3015) latch-up current .................................................... >200 ma selection guide range -55 -70 unit maximum access time 55 70 ns maximum operating current commercial 100 100 ma industrial 260 200 ma automotive-a 200 ma maximum cmos standby current commercial 15 15 ma industrial 30 30 ma automotive-a 30 ma operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial ?40 c to +85 c automotive-a ?40 c to +85 c electrical characteristics over the operating range parameter description test conditions -55 -70 unit min. max. min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc 2.2 v cc v v il input low voltage [1] ?0.5 0.8 ?0.5 0.8 v i ix input leakage current gnd < v i < v cc ?5 +5 ?5 +5 a i oz output leakage current gnd < v i < v cc , output disabled ?5 +5 ?5 +5 a i cc v cc operating supply current v cc = max.,i out = 0 ma com?l 100 100 ma ind?l 260 200 auto-a 200 i sb1 automatic ce 1 power?down current max. v cc , ce 1 > v ih, min. duty cycle=100% com?l 20 20 ma ind?l 50 40 auto-a 40 i sb2 automatic ce 1 power?down current max. v cc , ce 1 > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v com?l 15 15 ma ind?l 30 30 auto-a 30 capacitance [2] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 7 pf c out output capacitance 7 pf notes: 1. minimum voltage is equal to ?3.0v for pulse durations less than 30 ns. 2. tested initially and after any design or process changes that may affect these parameters.
cy6264 document #: 001-02367 rev. *a page 3 of 9 ac test loads and waveforms switching characteristics over the operating range [3] parameter description -55 -70 unit min. max. min. max. read cycle t rc read cycle time 55 70 ns t aa address to data valid 55 70 ns t oha data hold from address change 5 5 ns t ace1 ce 1 low to data valid 55 70 ns t ace2 ce 2 high to data valid 40 70 ns t doe oe low to data valid 25 35 ns t lzoe oe low to low z 3 5 ns t hzoe oe high to high z [4] 20 30 ns t lzce1 ce 1 low to low z [5] 5 5 ns t lzce2 ce 2 high to low z 3 5 ns t hzce ce 1 high to high z [4, 6] ce 2 low to high z 20 30 ns t pu ce 1 low to power-up 0 0 ns t pd ce 1 high to power-down 25 30 ns write cycle [6] t wc write cycle time 50 70 ns t sce1 ce 1 low to write end 40 60 ns t sce2 ce 2 high to write end 30 50 ns t aw address set-up to write end 40 55 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 25 40 ns t sd data set-up to write end 25 35 ns t hd data hold from write end 0 0 ns t hzwe we low to high z [4] 20 30 ns t lzwe we high to low z 5 5 ns notes: 3. test conditions assume signal transition ti me of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 4. t hzoe, t hzce , and t hzwe are specified with c l = 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 5. at any given temperature and voltage condition, t hzce is less than t lzce for any given device. 6. the internal write time of the memory is defined by the overlap of ce 1 low, ce 2 high, and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of th e signal that terminates the write. r1 481 ? 3.0v 5v output r1 481 ? r2 255 ? 30 pf gnd 90% 90% 10% < 5ns < 5 ns 5v output r2 255 ? 5 pf (a) (b) output 1.73v including jig and scope including jig and scope 10% equivalent to: thevenin equivalent all input pulses 167 ?
cy6264 document #: 001-02367 rev. *a page 4 of 9 switching waveforms read cycle no. 1 [7, 8] read cycle no. 2 [9, 10] notes: 7. device is continuously selected. oe , ce = v il . ce 2 = v ih. 8. address valid prior to or coincident with ce transition low. 9. we is high for read cycle. 10. data i/o is high z if oe = v ih , ce 1 = v ih , or we = v il . address data out previous data valid data valid t rc t aa t oha 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance impedance icc isb t hzoe t hzce t pd oe high data out v cc supply current ce 1 oe ce 2
cy6264 document #: 001-02367 rev. *a page 5 of 9 write cycle no. 1 (we controlled) [8, 10] write cycle no. 2 (ce controlled) [8, 10, 11] note: 11. if ce goes high simultaneously with we high, the output remains in a high-impedance state. switching waveforms (continued) data undefined high impedance t hd t hzwe t sd t lzwe t pwe t sa t ha t aw t sce2 t sce1 t wc data in data i/o address ce 1 oe we ce 2 data in valid t wc data undefined high impedance t aw t sa t pwe t ha t hd t hzwe t sd ce 2 we data in data i/o address t sce2 t sce1 ce 1 data in valid
cy6264 document #: 001-02367 rev. *a page 6 of 9 typical dc and ac characteristics ? 55 25 125 1.2 1.0 0.8 output source current (ma) ambient temperature (c) 0.6 0.4 0.2 0.0 i sb v cc =5.0v v in =5.0v i cc 1.2 1.4 1.0 0.6 0.4 0.2 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0 0.8 ? 55 25 125 normalized t aa 120 100 80 60 40 20 0.0 1.0 2.0 3.0 4.0 supply voltage (v) normalized supply current vs. supply voltage normalized access time vs. ambient temperature ambient temperature (c) normalized supply current vs. ambient temperature output voltage (v) output source current vs. output voltage 0.0 0.8 1.4 1.3 1.2 1.1 1.0 0.9 4.0 4.5 5.0 5.5 6.0 normalized t aa supply voltage (v) normalized access time vs. supply voltage 120 140 100 60 40 20 0.0 1.0 2.0 3.0 4.0 output sink current (ma) 0 80 output voltage (v) output sink current vs.output voltage i cc v cc =5.0v v cc =5.0v t a =25c v cc =5.0v t a =25c i sb t a =25c 0.6 0.8 0 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.0 2.0 3.0 4.0 normalized i po supply voltage(v) typical power-on current vs. supply voltage 30.0 25.0 20.0 15.0 10.0 5.0 0 200 400 600 800 delta t (ns) aa capacitance (pf) typical access time change vs. output loading 1.25 1.00 0.75 10 20 30 40 normalized i cc cycle frequency (mhz) normalized i cc vs. cycle time 0.0 5.0 0.0 1000 0.50 v cc =4.5v t a =25c v cc =5.0v t a =25c v cc =0.5v normalized i cc , i sb normalized i cc , i sb
cy6264 document #: 001-02367 rev. *a page 7 of 9 truth table ce 1 ce 2 we oe input/output mode h x x x high z deselect/power-down x l x x high z deselect l h h l data out read l h l x data in write l h h h high z deselect address designators address name address function pin number a4 x3 2 a5 x4 3 a6 x5 4 a7 x6 5 a8 x7 6 a9 y1 7 a10 y4 8 a11 y3 9 a12 y0 10 a0 y2 21 a1 x0 23 a2 x1 24 a3 x2 25
cy6264 document #: 001-02367 rev. *a page 8 of 9 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all products and company names mentioned in this docum ent may be the trademarks of their respective holders. ordering information speed (ns) ordering code package diagram package type operating range 55 cy6264-55snxc 51-85092 28-lead (300-mil narrow body) snc (pb-free) commercial cy6264-55snxi 28-lead (300-mil narrow body) snc (pb-free) industrial 70 cy6264-70snc 28-lead (300-mil narrow body) snc commercial cy6264-70snxc 28-lead (300-mil narrow body) snc (pb-free) cy6264-70sni 28-lead (300-mil narrow body) snc industrial cy6264-70snxi 28-lead (300-mil narrow body) snc (pb-free) cy6264-70snxa 28-lead (300-mil narrow body) snc (pb-free) automotive-a please contact your local cypress sales repres entative for availability of these parts package diagram dimensions in inches min. max. pin1id 0.291 0.300 0.463 0.477 0 .050 typ. 0.094 0.110 0.002 0.014 seating plane 0.008 0.012 0.702 0.710 0.020 0.042 0.004 0.014 0.020 0.020 0.015 0.032 0.026 a omedata cspi detail "a" 0.390 0.420 0.390 0.420 detail "b" b 51-85092-*b 28-lead (300 mil) snc package outline (narrow body) (51-85092)
cy6264 document #: 001-02367 rev. *a page 9 of 9 document history page document title: cy6264 8k x 8 static ram document number: 001-02367 rev. ecn no. issue date orig. of change description of change ** 384870 see ecn pci spec # change from 38-00425 to 001-02367 *a 488954 see ecn vkn added automotive product added 55 ns industrial spec removed soic package from the product offering changed the description of i ix from input load current to input leakage current in dc electrical characteristics table removed i os parameter from dc electrical characteristics table updated ordering information table
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